1. Field
Exemplary embodiments of the present invention relate to an integrated circuit and a memory device, and more particularly, to an integrated circuit and a memory device capable of performing a boot-up operation for transmitting data from a nonvolatile memory to latch circuits.
2. Description of the Related Art
FIG. 1 is a diagram illustrating a repair operation in a conventional memory device.
Referring to FIG. 1 the memory device includes a cell array 110 configured to include a plurality of memory cells, a row circuit 120 configured to activate a word line selected by a row address R_ADD, and a column circuit 130 configured to access for example, read or write a bit line selected by a column address C_ADD.
A row fuse circuit 140 stores a repair row address REPAIR_R_ADD corresponding to a fail memory cell within the cell array 110. A row comparison unit 150 compares the repair row address REPAIR_R_ADD with the row address R_ADD provided from the outside of the memory device. When the repair row address REPAIR_R_ADD is determined as identical with the row address R_ADD, the row comparison unit 150 controls the row circuit 120 to activate a redundancy word line instead of a word line designated by the row address R_ADD.
A column fuse circuit 160 stores a repair column address REPAIR_C_ADD corresponding to a fail memory cell within the cell array 110. A column comparison unit 170 compares the repair column address REPAIR_C_ADD with the column address C_ADD provided from the outside of the memory device. When the repair column address REPAIR_C_ADD is determined as identical with the column address C_ADD, the column comparison unit 170 controls the column circuit 130 to access a redundancy bit line instead of a bit line designated by the column address C_ADD.
Laser fuses are commonly used in the conventional fuse circuits 140 and 160. The laser fuse stores data of “high” or “low” depending on whether a fuse has been cut. The laser fuse is able to be programmed in a wafer state, but is unable to be programmed after a package is mounted on the inside of a package. Furthermore, the laser fuse is unable to be designed with a small area due to a limit to a pitch.
In order to overcome such disadvantages one of nonvolatile memory circuits, such as an E-fuse array circuit, NAND flash memory, NOR flash memory, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), ferroelectric RAM (FRAM), and magnetoresistive RAM (MRAM) as is included in a memory device. Repair information is stored in the nonvolatile memory circuit.
FIG. 2 is a diagram illustrating an example in which a nonvolatile memory circuit is used to store repair information in a memory device.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, repair registers 210_0 to 210_3 corresponding to the memory banks BK0 to BK3 and configured to store repair data, configuration registers 210_4 configured to store configuration data, a configuration circuit 220, and a nonvolatile memory circuit 201.
The nonvolatile memory circuit 201 corresponds to the fuse circuits 140 and 160 of FIG. 1. Repair addresses corresponding to all of the memory banks BK0 to BK3 are stored in the nonvolatile memory circuit 201. Furthermore, configuration data for the operation of the memory device is stored in the nonvolatile memory circuit 201. The nonvolatile memory circuit 201 may include any one of an E-fuse array circuit, NAND flash memory, NOR flash memory, EPROM, EEPROM, FRAM, and MRAM.
The repair registers 210_0 to 210_3 store the repair data of the memory banks BK0 to BK3 respectively. Furthermore, the configuration registers 210_4 store configuration data to be used in the configuration circuit 220. The configuration circuit 220 may configure various types of configuration values for the operation of the memory device for example, internal voltage levels and various types of latency based on the configuration data stored in the configuration registers 210_4. The repair registers and configuration registers 210_0 to 210_4 may store repair data during power-on of the memory device. Repair data and configuration data to be stored in the repair registers and configuration registers 210_0 to 210_4 are provided by the nonvolatile memory circuit 201. The nonvolatile memory circuit 201 sends repair data which are stored therein at a point in time at which a boot-up signal BOOTUP is enabled, to the repair registers 210_0 to 210_3, and sends configuration data to the configuration registers 210_4.
It takes additional time to fetch data stored in the nonvolatile memory circuit 201 due to long read latency of the nonvolatile memory circuit 201. Since data stored in the nonvolatile memory circuit 201 cannot be immediately fetched, it is impossible to perform a repair operation in a timely manner directly based on the data stored in the nonvolatile memory circuit 201. Therefore, repair data and configuration data stored in the nonvolatile memory circuit 201 are transmitted and stored in the repair registers and configuration registers 210_0 to 210_4. The repair data and configuration data stored in the repair registers and configuration registers 210_0 to 210_4 are used for the repair operation of the memory banks BK0 to BK3 and the configuration operation of the configuration circuit 220. The transmission process of the repair data and configuration data from the nonvolatile memory circuit 201 to the repair registers and configuration registers 210_0 to 210_4 is called a boot-up operation. Only when a boot-up operation is completed, will the memory device be able to start normal operations after repairing fail cells and performing various types of configuration operations.
When a memory device is tested, a burn-in test is commonly performed that applies stress by repeatedly driving the elements of the memory device. For the burn-in test on the memory banks BK0 to BK3 and the configuration circuit 220, the boot-up operation needs to be performed in advance. Data transmitted to the repair registers and configuration registers 210_0 to 210_4 as a result of the boot-up operation needs to remain intact. Accordingly, a burn-in test on the nonvolatile memory circuit 201 and a burn-in test on the memory banks BK0 to BK3 and the configuration circuit 220 are unable to be simultaneously performed. This becomes a major cause of a longer test time.